1. Technical Field
The present application generally relates to memory arrays and more particularly to circuits and methods for sensing, reading, and characterizing memory arrays.
2. Discussion of Related Art
As memory arrays have increased in size and developed in complexity, fabrication challenges have arisen. Specifically, it has become increasingly important to test and/or qualify specific electrical characteristics and parameters associated with the individual memory cells in large memory arrays. For example, it is often important to test the electrical characteristics and parameters including, but not limited to, minimum write voltages, minimum and maximum read voltages/currents (depending on the memory cell technology employed), minimum data-retention voltages (within volatile memory circuits), minimum data-retention times (within non-volatile memory technologies), and electrical noise tolerances. Each can be useful in gauging the performance of the individual memory cells and identifying faults and defects. Further, as the state of the art drives memory array circuits into increasingly complex structures—increasing memory array dimensions (the number of memory cells within an array) and decreasing physical dimensions of individual memory cells—the need to accurately and completely characterize such circuits becomes increasingly critical to optimizing the design and the long term reliability of such structures.
Resistive memory arrays have taken many forms. For example, carbon nanotube memory arrays disclosed by Bertin et al. in U.S. patent application Ser. No. 11/280,786, filed Nov. 15, 2005, entitled “Two-Terminal Nanotube Devices and Systems and Methods of Making Same” and, more particularly, carbon nanotube block memory arrays disclosed by Bertin et al., in U.S. patent application Ser. No. 11/835,856, entitled “Nonvolatile Nanotube Diodes and Nonvolatile Nanotube Blocks and Systems Using Same and Methods of Making Same” are comprised of multiple cells which can each be set (programmed) to a plurality of nonvolatile resistive states. Each aforementioned reference is herein incorporated by reference in its entirety. In other examples, resistive memory arrays can take the form of magneto-resistive memory arrays such as is disclosed in U.S. Pat. No. 6,999,340 to Shimizu. As disclosed in the aforementioned references, the memory cells can be set to a plurality of non-volatile resistive states and thus can be used to encode digital information. For example, a high resistive state can be used to indicate a digital “1” (or high) and a low resistive state can be used to indicate a digital “0” (or low). In a typical read operation, a sense current (sometimes referred to as a “read current” by those skilled in the art) is applied to a memory cell and the resulting voltage used to determine the resistive state of the cell.
A key parameter in resistive memory array circuits is the device's responsiveness to a given range of sense currents. In a typical sense current characterization operation, each cell within the memory array is written with a test value. Various electrical currents are then supplied to each memory cell within the memory array, and the resulting voltages analyzed to determine if the expected value was successfully read by each of the plurality of applied sense currents. In this way, the effectiveness of different sense currents can be characterized for the entire memory array.
While such a sense current characterization operation is effective in providing test information with regard to the effectiveness of different sense current values, such an operation can be limiting with respect to processing time. Characterizing a very large memory array with a significantly large set of sense current values (as is becoming increasingly common and necessary as the state of the art within nonvolatile memory devices advances) can become unacceptably costly and time consuming. To this end, a plurality of improved characterization and test methods have been proposed.
U.S. Pat. No. 7,106,644 to Chou teaches an improved circuit and associated test method for performing a burn in test on a memory array. A plurality of current limiting circuits are used to limit the current through each word line during the burn-in test, thus allowing a test voltage to sufficiently stress a plurality of word lines simultaneously.
U.S. Pat. No. 6,704,233 to Conte et al. teaches a circuit and associated method for reading a memory cell within a memory array. The circuit of Conte et al. comprises a reference memory cell, a current supply, a pair of transimpedance amplifiers, and a comparator. In the corresponding method Conte et al. generates and then passes a sense (read) current through both the memory cell under test and the reference memory cell, converting the currents through the memory cell under test and the reference memory cell to voltages (via the transimpedance amplifiers). Finally, the resulting voltages can be compared to obtain a digital representation of the bit stored in the memory cell under test.
U.S. Pat. No. 5,926,422 to Haukness teaches a circuit and associated method for rapidly testing a large memory array. A plurality of memory cells are sensed by a circuit which reports a digital value (a “high” or a “low”) indicating if all of the bits stored within said plurality of memory cells are of the same value. That is, Haukness' method significantly reduces the time required to verify a memory array by verifying the data state of a plurality of individual memory cells simultaneously.
While these methods reduce the amount of test time required within a characterization operation, they fail to provide the detailed test data obtained through a more traditional “brute force” sense current characterization operation.
Any discussion of the related art above and throughout this specification should in no way be considered as an admission that such art is widely known or forms part of the common general knowledge in the field.